The present disclosure relates generally to configuration of programmable devices, such as field programmable gate arrays (FPGAs). More particularly, the present disclosure relates to balanced and/or distributed configuration of programmable devices.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Integrated circuits (ICs) take a variety of forms, such as programmable devices. For instance, field programmable gate arrays (FPGAs) are programmable devices utilizing integrated circuits. Programmable devices may include logic that may be programmed (e.g., configured) post-manufacturing to provide various functionality input by a device owner rather than the device manufacturer. Thus, programmable devices contain programmable logic, or logic blocks, that may be configured to perform a variety of functions on the devices, according to a configured design.
The ICs may be configured in numerous different configurations. These configurations are generally loaded into configuration RAM (CRAM) using a single-direction communication bus or network that limits how quickly the configurations may be loaded into CRAM. For example, configuration of the ICs may be accomplished using a configuration network on chip (CNoC). A CNoC is based on one-way packet traffic that is generally routed in a single direction (e.g., horizontally) along rows of programmable units. This CNoC may be a bottleneck for configuration of the IC device. Moreover, when mirrored CNoCs are used in an IC device, the distribution of configuration may be imbalanced due to the purely one-directional communication of the CNoC.